Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning
نویسندگان
چکیده
منابع مشابه
Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning
Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits. In this paper, we a) provide a netlist-based circuit analysis technique to distinguish so-called critical configuration bits from essential bits in order to identify configuration bits ...
متن کاملDynamically Shifted Scrubbing for Fast Fpga Repair
Field Programmable Gate Arrays (FPGAs) are very successful platforms that rely on large configuration memories to store the circuit functions required by users. Faults affecting such memories are a major dependability threat for these devices, and the applicability of FPGAs on critical systems depends on efficient means to mitigate their effects. The usual means to effectively remove such fault...
متن کاملFast Local Scrubbing for FPGA’s Configuration Memory
Memory scrubbing is used to mitigate Single Event Upsets (SEUs) on susceptible devices. In the case of Field Programmable Gate Arrays (FPGAs), configuration memory scrubbing is generally used in conjunction with Triple Modular Redundancy (TMR) to increase reliability in spaceborne applications. Current solutions require a subsystem able to read and write from the configuration memory and retrie...
متن کاملConfiguration Caching Techniques for FPGA
Although run-time reconfigurable systems have been shown to achieve very high performance, the speedups over traditional microprocessor systems are limited by the cost of hardware configuration. In this paper, we explore the idea of configuration caching. We present techniques to carefully manage the configurations present on the reconfigurable hardware throughout program execution. Through the...
متن کاملMultiway Netlist Partitioning onto FPGA-based Board Architectures
FPGAs are well accepted as an alternative to ASICs and for rapid prototyping purposes. Netlists of designs which are too large to be implemented on a single FPGA, have to be mapped onto a set of FPGAs, which could be organized on an FPGA board containing various FPGAs connected by interconnection networks. This paper presents an efficient approach to the problem of multiway partitioning of larg...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Integration
سال: 2017
ISSN: 0167-9260
DOI: 10.1016/j.vlsi.2017.06.012